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ICS8430S10BYI-02 REVISION C JANUARY 17, 2011
13
2011 Integrated Device Technology, Inc.
ICS8430S10I-02 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Parameter Measurement Information, continued
Differential Cycle-to-Cycle Jitter
Period Jitter
RMS Phase Jitter
LVCMOS Cycle-to-Cycle Jitter
Half Period Jitter
LVCMOS Bank Skew (where X denotes QREF0 1, or 2)
tcycle n
tcycle n+1
tjit(cc) =
|tcycle n – tcycle n+1|
1000 Cycles
QA
nQA
VOH
VREF
VOL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
σ contains 68.26% of all measurements
2
σ contains 95.4% of all measurements
3
σ contains 99.73% of all measurements
4
σ contains 99.99366% of all measurements
6
σ contains (100-1.973x10-7)% of all measurements
Histogram
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise
P
o
w
er
V
DDOX
2
V
DDOX
2
V
DDOX
2
tcycle n
tcycle n+1
tjit(cc) =
|tcycle n – tcycle n+1|
1000 Cycles
QBx, QC,
QDx, QE,
QREFx
t half period n
t half period n + 1
1
f
o
t jit(hper) = t half period n — 1
2*f
o
QA
nQA
tsk(b)
V
DDOX
2
V
DDOX
2
QREFx
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